Leakage and Variation Aware Thermal Management of Nanometer Scale Ics

For sub-100 nm CMOS technologies, leakage power forms a significant component of the total power dissipation, especially due to within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). Since leakage power and operating temperature are electrothermally coupled to each other, increasing power dissipation and thermal problems are becoming key concerns not only from a thermal management point of view but also because most reliability mechanisms are highly temperature sensitive. This paper provides an overview of a novel methodology for making temperature and reliability aware power/performance/cooling-cost tradeoffs in leakage dominant nanometer scale high-performance ICs. First, a framework to accurately estimate subthreshold leakage under both within-die and die-to-die parameter variations is outlined. It is shown that die-to-die temperature variations can significantly increase leakage power, mainly because of electrothermal couplings between power and temperature. Next, a recently developed self-consistent electrothermal methodology to accurately estimate the junction temperature is presented and is shown to be significant for thermal management of leakage and variation dominant CMOS technologies. The methodology is then applied to provide a reliability and thermally aware design space that can be used to optimize and compare various designs.